1. Field of the Invention
The present invention relates to a method of filling a bit line contact via, and more specifically to a method of forming a conductive layer in the bit line contact via.
2. Description of the Related Art
FIGS. 1A through 1H are cross-sections illustrating a conventional method of filling a bit line contact via.
In FIG. 1A, first, a substrate 100, such as single crystalline silicon, having a device region 101, periphery region 102, and periphery region 103 is provided. The device region 101 has a transistor structure having a gate electrode 120 protruding from an active surface of substrate 100. A drain region 112 and source region 114 are disposed on the active surface on both sides of the gate electrode 120 respectively. Gate electrode 120 is a word line, having a multi-level structure as desired. For example, gate electrode 120 in FIG. 1A has gate dielectric layer 121, polycrystalline silicon layer 122 and metal silicide layer 123 as conductive layers, and hard mask layer 124 sequentially or the active surface of substrate 100. Periphery region 103 has the same multi-level structure as that of gate electrode 120. A patterned resist layer 191 overlying substrate exposes device region 101. The drain region 112 is doped with a dopant 10, usually an element in either group 13 (IIIA) or 15 (VA) of the periodic table such as As, by ion implantation in order to decrease the contact impedance of bit line contact when a conductive layer is subsequently formed on drain region 112.
In FIG. 1B, the patterned resist layer 191 is removed when ion implantation is completed. A silicon nitride layer is then formed on substrate 100 and patterned to form a spacer 125 on the sidewall of gate electrode 120. Further, if the recipe is not properly controlled during ion implantation, the dopant 10 in drain region 112 and source region 114 will diffuse, resulting in an extended drain region 112 and source region 114, thereby shortening the channel region between drain region 112 and source region 114.
In FIG. 1C, a dielectric layer 130 and patterned resist layer 192 are sequentially formed on substrate 100. The patterned resist layer 192 has openings 192a through 192c exposing a part of dielectric layer 130 respectively.
In FIG. 1D, the exposed dielectric layer 130 is removed by anisotropic etching using patterned resist layer 192 as an etching mask, forming a via 131 exposing drain region 112 as a bit line contact via, via 132 exposing substrate 100 as a contact via of periphery region 102, and via 133a exposing hard mask layer 124. The patterned resist layer 192 is then removed.
In FIG. 1E, a patterned resist layer 193 is formed on substrate 100. The patterned resist layer 193 has an opening 193a, approximately as large as via 133a, directly above via 133a, exposing the hard mask layer 124 in periphery region 103.
In FIG. 1F, the exposed hard mask layer 124 is removed by anisotropic etching using patterned resist layer 193 as an etching mask. Thus, via 133, exposing metal silicide layer 123, is formed as a contact via of periphery region 103. The patterned resist layer 193 is then removed.
In FIG. 1G, a conductive barrier layer 140 is conformally formed on the exposed active surface of substrate 100, avoiding the inter-diffusion between a subsequently formed conductive layer and every drain region 112 exposed by via 131, substrate 100 exposed by via 132, and metal silicide layer 123 exposed by via 133 which can negatively affect the electrical performance and reliability of the end product. The barrier layer 140, usually has a conductive TiN layer, formed by forming a Ti layer on the exposed active surface of substrate 100 using sputtering, and annealing substrate 100 in a nitrogen atmosphere.
In FIG. 1H, a tungsten layer is filled in vias 131 through 133 by chemical vapor deposition (CVD) as bit line contact and periphery contact.
As described in FIGS. 1A and 1B, the channel region between drain region 112 and source region 114 is shortened resulting from the extension of drain region 112 and source region 114. Therefore, exerting a lower voltage between drain region 112 and source region 114 can cause electric conduction, thereby negatively affecting the electric performance of device region 101.
Further, the sputtering step during formation of barrier layer 140 damages the lattice structure of drain region 112, resulting in unwanted carriers remaining in the drain region 112, thereby further negatively affecting electrical performance and reliability of the end product.